IRFI1310N preliminary hexfet ? power mosfet pd - 9.1611a s d g v dss = 100v r ds(on) = 0.036 w i d = 24a l advanced process technology l isolated package l high voltage isolation = 2.5kvrms ? l sink to lead creepage dist. = 4.8mm l fully avalanche rated to-220 fullpak parameter typ. max. units r q jc junction-to-case CCC 2.7 r q ja junction-to-ambient CCC 65 thermal resistance fifth generation hexfets from international rectifier utilize advanced processing techniques to achieve extremely low on-resistance per silicon area. this benefit, combined with the fast switching speed and ruggedized device design that hexfet power mosfets are well known for, provides the designer with an extremely efficient and reliable device for use in a wide variety of applications. the to-220 fullpak eliminates the need for additional insulating hardware in commercial-industrial applications. the moulding compound used provides a high isolation capability and a low thermal resistance between the tab and external heatsink. this isolation is equivalent to using a 100 micron mica barrier with standard to-220 product. the fullpak is mounted to a heatsink using a single clip or by a single screw fixing. 3/16/98 description parameter max. units i d @ t c = 25c continuous drain current, v gs @ 10v 24 i d @ t c = 100c continuous drain current, v gs @ 10v 17 a i dm pulsed drain current ?? 140 p d @t c = 25c power dissipation 56 w linear derating factor 0.37 w/c v gs gate-to-source voltage 20 v e as single pulse avalanche energy ?? 420 mj i ar avalanche current ?? 22 a e ar repetitive avalanche energy ? 5.6 mj d v /d t peak diode recovery dv/dt ?? 5.0 v/ns t j operating junction and -55 to + 175 t stg storage temperature range soldering temperature, for 10 seconds 300 (1.6mm from case ) c mounting torque, 6-32 or m3 screw 10 lbf?in (1.1n?m) absolute maximum ratings c/w
IRFI1310N parameter min. typ. max. units conditions v (br)dss drain-to-source breakdown voltage 100 CCC CCC v v gs = 0v, i d = 250a d v (br)dss / d t j breakdown voltage temp. coefficient CCC 0.11 CCC v/c reference to 25c, i d = 1ma ? r ds(on) static drain-to-source on-resistance CCC CCC 0.036 w v gs = 10v, i d = 13a ? v gs(th) gate threshold voltage 2.0 CCC 4.0 v v ds = v gs , i d = 250a g fs forward transconductance 14 CCC CCC s v ds = 25v, i d = 22a ? CCC CCC 25 a v ds = 100v, v gs = 0v CCC CCC 250 v ds = 80v, v gs = 0v, t j = 150c gate-to-source forward leakage CCC CCC 100 v gs = 20v gate-to-source reverse leakage CCC CCC -100 na v gs = -20v q g total gate charge CCC CCC 120 i d = 22a q gs gate-to-source charge CCC CCC 15 nc v ds = 80v q gd gate-to-drain ("miller") charge CCC CCC 58 v gs = 10v, see fig. 6 and 13 ?? t d(on) turn-on delay time CCC 11 CCC v dd = 50v t r rise time CCC 56 CCC i d = 22a t d(off) turn-off delay time CCC 45 CCC r g = 3.6 w t f fall time CCC 40 CCC r d = 2.9 w, see fig. 10 ?? between lead, CCC CCC 6mm (0.25in.) from package and center of die contact c iss input capacitance CCC 1900 CCC v gs = 0v c oss output capacitance CCC 450 CCC v ds = 25v c rss reverse transfer capacitance CCC 230 CCC ? = 1.0mhz, see fig. 5 ? c drain to sink capacitance CCC 12 CCC ? = 1.0mhz nh electrical characteristics @ t j = 25c (unless otherwise specified) l d internal drain inductance l s internal source inductance CCC CCC s d g i gss ns 4.5 7.5 i dss drain-to-source leakage current pf notes: ? repetitive rating; pulse width limited by max. junction temperature. ( see fig. 11 ) ? starting t j = 25c, l = 1.0mh r g = 25 w , i as = 22a. (see figure 12) ? t=60s, ?=60hz ? i sd 22a, di/dt 180a/s, v dd v (br)dss , t j 175c ? uses irf1310n data and test conditions ? pulse width 300s; duty cycle 2%. s d g parameter min. typ. max. units conditions i s continuous source current mosfet symbol (body diode) CCC CCC showing the i sm pulsed source current integral reverse (body diode) ?? CCC CCC p-n junction diode. v sd diode forward voltage CCC CCC 1.3 v t j = 25c, i s = 13a, v gs = 0v ? t rr reverse recovery time CCC 180 270 ns t j = 25c, i f = 22a q rr reverse recoverycharge CCC 1.2 1.8 c di/dt = 100a/s ?? t on forward turn-on time intrinsic turn-on time is negligible (turn-on is dominated by l s +l d ) source-drain ratings and characteristics a 24 140
IRFI1310N fig 4. normalized on-resistance vs. temperature fig 2. typical output characteristics fig 1. typical output characteristics fig 3. typical transfer characteristics 1 10 100 1000 0.1 1 10 100 20us pulse width t = 25 c j o top bottom vgs 15v 10v 8.0v 7.0v 6.0v 5.5v 5.0v 4.5v v , drain-to-source voltage (v) i , drain-to-source current (a) ds d 4.5v 1 10 100 1000 0.1 1 10 100 20us pulse width t = 175 c j o top bottom vgs 15v 10v 8.0v 7.0v 6.0v 5.5v 5.0v 4.5v v , drain-to-source voltage (v) i , drain-to-source current (a) ds d 4.5v 1 10 100 1000 4.0 5.0 6.0 7.0 8.0 9.0 10.0 v , gate-to-source voltage (v) i , drain-to-source current (a) gs d t = 25 c j o t = 175 c j o -60 -40 -20 0 20 40 60 80 100 120 140 160 180 0.0 0.5 1.0 1.5 2.0 2.5 3.0 t , junction temperature ( c) r , drain-to-source on resistance (normalized) j ds(on) o v = i = gs d 10v 36a
IRFI1310N fig 6. typical gate charge vs. gate-to-source voltage fig 8. maximum safe operating area fig 5. typical capacitance vs. drain-to-source voltage fig 7. typical source-drain diode forward voltage 1 10 100 0 500 1000 1500 2000 2500 3000 3500 v , drain-to-source voltage (v) c, capacitance (pf) ds v c c c = = = = 0v, c c c f = 1mhz + c + c c shorted gs iss gs gd , ds rss gd oss ds gd c iss c oss c rss 0 20 40 60 80 100 120 0 4 8 12 16 20 q , total gate charge (nc) v , gate-to-source voltage (v) g gs for test circuit see figure i = d 13 22a v = 20v ds v = 50v ds v = 80v ds 0.1 1 10 100 1000 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 v ,source-to-drain voltage (v) i , reverse drain current (a) sd sd v = 0 v gs 1 10 100 1000 1 10 100 1000 operation in this area limited by r ds(on) single pulse t t = 175 c = 25 c j c o o v , drain-to-source voltage (v) i , drain current (a) i , drain current (a) ds d 10us 100us 1ms 10ms
IRFI1310N fig 10a. switching time test circuit v ds 90% 10% v gs t d(on) t r t d(off) t f fig 10b. switching time waveforms v ds pulse width 1 s duty factor 0.1 % r d v gs r g d.u.t. 10v + - v dd fig 11. maximum effective transient thermal impedance, junction-to-case fig 9. maximum drain current vs. case temperature 0.01 0.1 1 10 0.00001 0.0001 0.001 0.01 0.1 1 10 notes: 1. duty factor d = t / t 2. peak t = p x z + t 1 2 j dm thjc c p t t dm 1 2 t , rectangular pulse duration (sec) thermal response (z ) 1 thjc 0.01 0.02 0.05 0.10 0.20 d = 0.50 single pulse (thermal response) 25 50 75 100 125 150 175 0 5 10 15 20 25 t , case temperature ( c) i , drain current (a) c d
IRFI1310N q g q gs q gd v g charge d.u.t. v ds i d i g 3ma v gs .3 m f 50k w .2 m f 12v current regulator same type as d.u.t. current sampling resistors + - 10 v fig 13b. gate charge test circuit fig 13a. basic gate charge waveform fig 12c. maximum avalanche energy vs. drain current 25 50 75 100 125 150 175 0 200 400 600 800 1000 starting t , junction temperature ( c) e , single pulse avalanche energy (mj) j as o i d top bottom 9.0a 16a 22a fig 12b. unclamped inductive waveforms fig 12a. unclamped inductive test circuit t p v (br)dss i as r g i as 0.01 w t p d.u.t l v ds + - v dd driver a 15v 20v
IRFI1310N p.w. period di/dt diode recovery dv/dt ripple 5% body diode forward drop re-applied voltage reverse recovery current body diode forward current v gs =10v v dd i sd driver gate drive d.u.t. i sd waveform d.u.t. v ds waveform inductor curent d = p. w . period + - + + + - - - fig 14. for n-channel hexfets * v gs = 5v for logic level devices peak diode recovery dv/dt test circuit ? ? ? r g v dd dv/dt controlled by r g driver same type as d.u.t. i sd controlled by duty factor "d" d.u.t. - device under test d.u.t circuit layout considerations low stray inductance ground plane low leakage inductance current transformer ? *
IRFI1310N part number international rectifier logo example : this is an irf1010 w ith assembly lot co de 9b1m assembly lot co de date code (yyw w ) yy = year ww = week 9246 irf1010 9b 1m a part marking information to-220 fullpak package outline to-220 fullpak outline dimensions are shown in millimeters (inches) lead assignments 1 - g ate 2 - d ra in 3 - so u rc e notes: 1 dimensioning & tolerancing per ansi y14.5m, 1982 2 controlling dimension: inch. d c a b minimum creepage distance betw een a-b-c-d = 4.80 (.189) 3x 2.85 (.112) 2.65 (.104) 2.80 (.110) 2.60 (.102) 4.80 (.189) 4.60 (.181) 7.10 (.280) 6.70 (.263) 3.40 (.133) 3.10 (.123) ? - a - 3.70 (.145) 3.20 (.126) 1.15 (.045) m in . 3.30 (.130) 3.10 (.122) - b - 0.90 (.035) 0.70 (.028) 3x 0.25 (.010) m a m b 2.54 (.100) 2x 3x 13.70 (.540) 13.50 (.530) 16.00 (.630) 15.80 (.622) 1 2 3 10.60 (.417) 10.40 (.409) 1.40 (.055) 1.05 (.042) 0.48 (.019) 0.44 (.017) part number international rectifier lo go date code (yyw w ) yy = year ww = week assembly lot co de e401 9245 irfi840g exam ple : th is is an ir fi840g w ith assem bly lo t co d e e401 a world headquarters: 233 kansas st., el segundo, california 90245, tel: (310) 322 3331 european headquarters: hurst green, oxted, surrey rh8 9bb, uk tel: ++ 44 1883 732020 ir canada: 7321 victoria park ave., suite 201, markham, ontario l3r 2z8, tel: (905) 475 1897 ir germany: saalburgstrasse 157, 61350 bad homburg tel: ++ 49 6172 96590 ir italy: via liguria 49, 10071 borgaro, torino tel: ++ 39 11 451 0111 ir far east: k&h bldg., 2f, 30-4 nishi-ikebukuro 3-chome, toshima-ku, tokyo japan 171 tel: 81 3 3983 0086 ir southeast asia: 315 outram road, #10-02 tan boon liat building, singapore 0316 tel: 65 221 8371 http://www.irf.com/ data and specifications subject to change without notice. 3/98
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